[新連載]CPLD入門!
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いつか使うことになるだろうと思ってはいたのですが。
何を今頃になって、というようなものですが。
ようやく本気で、CPLDと四つに取り組みます。
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[第51回]
●VHDLプログラムリスト(ざっと説明その2)
前回からの続きです。
次はcntr3です。
--cntr3 process(hblnkwk) begin if hblnkwk'event and hblnkwk = '1' then cntr3 <= cntr3 +"000000001"; end if; if cntr3="111000001" then cntr3<="000000000"; end if; end process; |
-- vblnk,vsync process(cntr3) begin --vblnkwk if cntr3(8)='0' then vblnkwk<='1'; elsif cntr3(8 downto 4)="11001" then vblnkwk<='0'; end if; --vsyncwk if cntr3="110011100" then vsyncwk<='0'; elsif cntr3="110011110" then vsyncwk<='1'; end if; end process; |
--ramadrs process(cntr2,cntr3,vblnkwk) begin if vblnkwk='0' then ramadrswk<="0000000"; ramadrswk0<="0000000"; elsif cntr3(3 downto 0)="1111" and hblnkwk = '0' then ramadrswk0 <= ramadrswk; elsif cntr2="1010000" and cntr1(0)='1' then ramadrswk <= ramadrswk0; elsif cntr2(3)'event and cntr2(3)='0' and hblnkwk='1' then ramadrswk<=ramadrswk+"0000001"; end if; end process; |
-- address select -- vrams process(MREQ,MWR) begin if MREQ='0' and MWR='0' and A11_15="11111" and vrams2='0' then VRAMS<='0'; AHout<=AHin; ALout<=ALin; VRAMWR<=MWR; else VRAMS<='1'; AHout<=ramadrswk; ALout<=cntr2(3 downto 0); VRAMWR<='1'; end if; end process; |
-- vblnk read -- i/o active vrams vactive process(Resetin,AHin,ALin,IOWR) begin if Resetin='0' then vrams2<='1'; vactive<='1'; elsif AHin(3 downto 0)="1101" and ALin(3 downto 2)="00" and IOWR='0' then vrams2<=not D0IN; vactive<=not D1IN; end if; end process; --see note 5/6 process(AHin,ALin,IORD) begin if AHin(3 downto 0)="1101" and ALin(3 downto 2)="00" and IORD='0' and vblnkwk='0' then D7OUT<='0'; else D7OUT<='Z'; end if; end process; |
rgbout<=sftrgstr(7) and hblnkwk2 and vblnkwk and vactive; RGB_ROUT<=rgbout; RGB_GOUT<=rgbout; RGB_BOUT<=rgbout; ROMadrs<=cntr3( 3 downto 1); end rtl; |